Integrated Clock Filter IP Product Brief - This product brief describes the Multi-Channel Clock Filter IP Core, a high-performance timing solution that generates jitter-compliant TX clocks for multiple signal protocols on Agilex® 7 FPGA FGT transceivers. Optimized for OTN multiplexers and regenerators, the IP dynamically filters and smooths gapped clock inputs through embedded DCXO control to ensure accurate clock recovery and protocol-compliant jitter performance. - 2026-05-06

Version

1.0

Product Type

Device Families > Agilex Families > Agilex 7 > F-Series

Device Families > Agilex Families > Agilex 7 > I-Series

Device Families > Agilex Families > Agilex 7 > M-Series

Resource Type

Documentation > Briefs

Source Name

UD