Agilex® 7 FPGA F-Tile SDI II FPGA IP Multi Rate Parallel Loopback Without External VCXO Onboard Tutorial Example Design User Guide - This document showcases a multi-rate parallel loopback without external VCXO onboard design implemented on the Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit. The design demonstrates SDI loopback functionality using the SDI II FPGA IP.