Altera® I/O Limited FPGAs and SoCs Technical Brief - Describes I/O Limited (IOL) FPGAs and SoCs that limit transceiver bandwidth to <500 Gbps and I/O usage to ≤700 pins. These devices are ideal for export-controlled applications where higher transceiver or I/O utilization is restricted. - 2026-09-01

Version

2026.09.01

Product Type

Device Families > Stratix Families > Stratix 10

Device Families > Arria Families > Arria 10

Device Families > Agilex Families > Agilex 5 > D-Series

Device Families > Agilex Families > Agilex 5 > E-Series

Device Families > Agilex Families > Agilex 7 > F-Series

Device Families > Agilex Families > Agilex 7 > I-Series

Device Families > Agilex Families > Agilex 7 > M-Series

Resource Type

Documentation > Briefs

Source Name

UD