Clock Networks and PLLs in Arria® II Devices - Arria® II Device Handbook, Volume 1, Chapter 5 - This chapter describes the hierarchical clock networks and phase-locked loops (PLLs) which have advanced features in Arria® II devices that provide dedicated global clock networks (GCLKs), regional clock networks (RCLKs), and periphery clock networks (PCLKs). - 2012-07-05
aiigx_51005.pdf
- Version
- 4.2
- Product Type
- Device Families > Arria Families > Arria II
- Resource Type
- Documentation > User Guides
- Source Name
- UD