Cyclone® IV Device Handbook, Volume 1, Chapter 5: Clock Networks and PLLs - Describes the hierarchical clock networks and phase locked loops (PLLs). Reconfigure the PLL counter clock frequency and phase shift in real time and dynamically adjust the output clock phase shift. - 2012-09-30
cyiv-51005.pdf
- Version
- 2.4
- Product Type
- Device Families > Cyclone Families > Cyclone IV
- Resource Type
- Documentation > User Guides
- Source Name
- UD