Generating Functionally Equivalent FPGAs and ASICs With a Single Set of RTL and Synthesis/Timing Constraints - Altera first introduced the 180-nm CMOS-technology HardCopy® series of ASICs, with their “seamless prototyping” capabilities, in 2001. The premise behind this first-generation HardCopy ASIC product was to “harden” the look-up table (LUT) structure of the FPGA and replace the programmable switch fabric with a direct wire (ASIC) - 2009-02-18
wp-01095-rtl-synthesis-timing.pdf
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