Why does the Viterbi IP core output incorrect data when sink_val signal is not constantly driven high? - Why does the Viterbi IP core output incorrect data when sink_val signal is not constantly driven high? Description Due to a problem with the Intel® Quartus® Prime software version 16.0 and 16.1, you may encounter the above problem if the sink_val signal of the Viterbi IP core is not constantly driven high. Resolution This problem has been fixed in the Intel Quartus Prime software version 17.0. Custom Fields values: ['novalue'] Troubleshooting FB: 445279; False ['Viterbi IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 17.0 16.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']