Incorrect Numbering of 256-Bit Interface in PCI Express Compiler User Guide - Incorrect Numbering of 256-Bit Interface in PCI Express Compiler User Guide Description The bit ordering is reversed in the figure Location of Headers and Data for Avalon-ST 256-Bit Interface, in the PCI Express Compiler User Guide . Bit 0 should be at the bottom of the figure and Bit 255 at the top. This is a documentation error only. Resolution No workarounds are required. This issue is fixed in version 11.0 of the Stratix V Hard IP for PCI Express User Guide . Starting in the Quartus II software release 11.0, the IP Compiler for PCI Express does not support Stratix V devices. Stratix V device support is now moved to the Stratix V Hard IP for PCI Express. The relevant figure in version 11.0 of the new user guide is Figure 5-29. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 11.0 10.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']