Why is ODT asserted for more than one rank in my DDR3 UniPHY controller? - Why is ODT asserted for more than one rank in my DDR3 UniPHY controller? Description If you have a multi-rank DDR3 UniPHY controller generated in the Quartus® II software version 12.1SP1 or later, you may see the ODT signals for multiple ranks assert simultaneously. There is a problem with ODT when the Memory format in the Memory Parameters tab of the MegaWizard™ Plug-In Manager is set to Discrete Device. Resolution The workaround is to change the Memory Format in the Memory Parameters tab to UDIMM. This problem is fixed starting with the Quartus® II software version 15.0. Custom Fields values: ['novalue'] Troubleshooting 1408190888 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 15.0 12.1.1 ['Stratix® III FPGAs', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']