Can I run a VHDL simulation for my Root Port Avalon-MM design under NCSim? - Can I run a VHDL simulation for my Root Port Avalon-MM design under NCSim? Description When you try to compile the auto-generated PCI® Express Hard IP Root port VHDL testbench using NCSim, you may see errors such as the following: ncvhdl_p: *E,EXPTYP (./..//pcie_tb/simulation/pcie_tb.vhd,1459|10): ncelab: *F,EVNMRA: the entity specified \'WORK.PCIE_TB\' has no architecture Resolution VHDL simulation is not supported for Root Port variants under NCSim. This is not scheduled to be fixed in a future Quartus® software release. Custom Fields values: ['novalue'] Troubleshooting 286702 False ['PCI Express'] ['FPGA Dev Tools Quartus II Software'] novalue 14.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']