Does direct connection of two AXI4 Masters to DDR Slave support auto-arbitration on Agilex 5? - Does direct connection of two AXI4 Masters to DDR Slave support auto-arbitration on Agilex 5? Hi all, I'm developing on the Agilex 5 platform and need two AXI4 masters to access the DDR. I noticed there isn't a standalone IP similar to Xilinx's axi_interconnect. Is it correct to simply connect two AXI masters directly to the single DDR AXI slave port (as shown below)? Will the interconnect fabric generate the necessary arbitration and routing logic in this case？ Replies: Re: Does direct connection of two AXI4 Masters to DDR Slave support auto-arbitration on Agilex 5? The issue has been resolved. The root cause was that parameters from the upstream module were not propagated correctly, which caused this specific Master path to be optimized away during synthesis. Thank you all for your suggestions Replies: Re: Does direct connection of two AXI4 Masters to DDR Slave support auto-arbitration on Agilex 5? Hi wangduoyu , What type of synthesis away warning you got? Did you run the read and write test with AXI_master1? Maybe you can add attribute "/* synthesis preserve */" to the register? https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vlog/vlog_file_dir_preserve.htm Regards, Adzim Replies: Re: Does direct connection of two AXI4 Masters to DDR Slave support auto-arbitration on Agilex 5? It's hard to see because your screenshots don't enlarge in the forum, but how are you seeing that a whole EMIF is getting optimized away? There may be more than one interconnect. Did you check the other interconnects from the popup there in the viewer? As for the addressing, I was just referring to the base (starting address) that can be set independently between the two separate manager interfaces, not the span of the memory (which as mentioned is fixed based on density). If they both start at 0x0, which they would by default, then that's fine. Replies: Re: Does direct connection of two AXI4 Masters to DDR Slave support auto-arbitration on Agilex 5? Hi, I followed your advice and configured the arbitration priorities for the two masters, but I am encountering a new issue. When both AXI masters are connected directly to the EMIF simultaneously, the logic for 'AXI_master1' is consistently optimized away during synthesis. However, when I connect each master individually, they both function correctly. This strongly suggests a potential issue with the arbitration or routing logic within the generated mm_interconnect. Do you have any suggestions for resolving this? Is it strictly required that the address maps for the two masters be non-overlapping? As you mentioned in my other thread, should I be using an address_span_extender to explicitly segregate the address spaces of the two masters? Replies: Re: Does direct connection of two AXI4 Masters to DDR Slave support auto-arbitration on Agilex 5? Hi wangduoyu , The address range already set correctly. It's referring to address range of the DDR that the master can access. Both master will have same address range in this case. If you like to set a priority to one of the AXI master, you can modify the Arbitration Share in the Platform Designer. If you right click on the signal and check on Show Arbitration Share, the arbitration priority will be displayed. You can increase the number if you like to prioritize the module. Here the reference: https://www.intel.com/content/www/us/en/docs/programmable/683609/25-1-1/arbitration-shares-and-bursts.html Regards, Adzim Replies: Re: Does direct connection of two AXI4 Masters to DDR Slave support auto-arbitration on Agilex 5? Hi, As shown in the screenshot below, the address ranges for these two AXI Masters are automatically assigned based on the EMIF's "Die Density" parameter. My current configuration is: Total DDR Density = 8Gb x 2 Channels = 16Gb (2GB). Consequently, Platform Designer automatically maps both AXI Masters to the address range 0x0000_0000 - 0x7FFF_FFFF. If I attempt to manually modify this range, the system reports an "address out of range" error. Could you please advise on how to handle this situation correctly? Thanks Replies: Re: Does direct connection of two AXI4 Masters to DDR Slave support auto-arbitration on Agilex 5? What are you seeing on the Address Map tab? You have to select the manager from the list on the left to see its address map. Every host/manager has its own address map. Replies: Re: Does direct connection of two AXI4 Masters to DDR Slave support auto-arbitration on Agilex 5? Thanks. Is it necessary to use an AXI Bridge to solve the addressing issue? Currently, my custom defined AXI Master shows no options in the Address Map tab, even after I connect it to the DDR in the System View Replies: Re: Does direct connection of two AXI4 Masters to DDR Slave support auto-arbitration on Agilex 5? This is helpful. Replies: Re: Does direct connection of two AXI4 Masters to DDR Slave support auto-arbitration on Agilex 5? Yes, this is how it should work. Be sure to check the addressing for both of those AXI managers on the Address Map tab to make sure the EMIF is at the address location you want, especially if it should be different for the two managers.