Why do I see functional problems in my clocked video input (cvi) module? - Why do I see functional problems in my clocked video input (cvi) module? Description You may see functional(hardware) problems for the CVI module for designs created using the Quartus® II software versions 13.0 and earlier as internal timing violations may be masked by an incorrect set_false_path constraint in the automatically generated sdc file. The following incorrect set_false_path constraint cuts all timing withinn the fifo. set_false_path -to [get_keepers {*alt_vipcti130_Vid2IS:*|alt_vipcti130_common_fifo:*}] Resolution This problem is resolved in the Quartus II software version 13.0SP1 where the constraint is replaced with the following specific false_path constraints: set_false_path -from [get_registers {*alt_vipcti*_Vid2IS:*|*_common_fifo:*dcfifo*delayed_wrptr_g[*]}] -to [get_registers {*alt_vipcti*_Vid2IS:*|*_common_fifo:*dcfifo*rs_dgwp*}] set_false_path -from [get_registers {*alt_vipcti*_Vid2IS:*|*_common_fifo:*dcfifo*rdptr_g[*]}] -to [get_registers {*alt_vipcti*_Vid2IS:*|*_common_fifo:*dcfifo*ws_dgrp*}] Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.0.1 novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']