Unable to Bring-Up Individual Transceiver Channel - Unable to Bring-Up Individual Transceiver Channel Description You may not be able to bring up individual transceiver channel for designs that include FIFO-less multiport MAC with PCS and embedded PMA in GIGE mode. Resolution Turn on the Enable SGMII bridge logic parameter in the designs. Edit the following in altera_tse_multi_mac_pcs_pma_gige.v: Replace .rx_digitalreset with .rx_digitalreset (rx_digitalreset_sqcnr_5) in the altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_5 module . Replace .pll_is_locked with .pll_is_locked(locked_signal_21) in the altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_21 module. Replace .pll_is_locked with .pll_is_locked(locked_signal_22) in the ltera_tse_reset_sequencer altera_tse_reset_sequencer_inst_22 module. However, this workaround does not work for designs targeting Stratix V and above. This issue will be fixed in a future version of the Triple-Speed Ethernet MegaCore function. Custom Fields values: ['novalue'] Troubleshooting novalue True ['Ethernet'] ['FPGA Dev Tools Quartus II Software'] novalue 11.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']