Why do I see that mem_reset_n and mem_cke assertion does not meet the JEDEC specification at Intel® Arria®10 FPGA DDR4, DDR3 IP EMIF IP simulation? - Why do I see that mem_reset_n and mem_cke assertion does not meet the JEDEC specification at Intel® Arria®10 FPGA DDR4, DDR3 IP EMIF IP simulation? Description You might see the DDR4 and DDR3 initializing sequence timing violation where JEDEC specification defines 500us at simulation. Resolution This is to shorten the simulation time and the actual hardware follows the JEDEC specification. Custom Fields values: ['novalue'] Troubleshooting 2205916448 False ['External Memory Interfaces Arria® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 16.1 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']