Timing setup violations in SerialLite III Streaming IP Core Design Example - Timing setup violations in SerialLite III Streaming IP Core Design Example Description The SerialLite III Streaming IP Core design example will run into timing setup violations in ACDS Quartus II version 15.0 due to the removal of false path in the seriallite_iii_streaming_demo.sdc file. Resolution Manually update the seriallite_iii_streaming_demo.sdc with the following constraint: set_false_path -to [get_cells -compatibility *demo_mgmt*dp_sync_stage_1|o[*]] Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 15.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue'] - 2021-08-25