Why do I see a calibration failure when using the UniPHY DDR2 full-rate controller in Stratix V? - Why do I see a calibration failure when using the UniPHY DDR2 full-rate controller in Stratix V? Description Due to a problem in the Quartus® II software version 14.1, 15.0 and 15.1, you may observe a calibration failure when using the UniPHY DDR2 full-rate controller in Stratix® V. The calibration failure occurs because of incorrect settings for the DQ and DQS enable signals in the generated programming file (.sof) which causes the DQ and DQS signals to not toggle properly when running on hardware. Resolution This issue will be fixed in a future version of Quartus Prime software. Alternatively, use a DDR2 half-rate controller. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 16.0 14.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']