Do Arria V devices have similar I/O placement restrictions with HSTL and SSTL pins as compared to Arrix II GX devices? - Do Arria V devices have similar I/O placement restrictions with HSTL and SSTL pins as compared to Arrix II GX devices? Description No, Arria® V devices do not have similar I/O placement restrictions with HSTL and SSTL pins as compared to Arrix II GX devices. You may utilize all available HSTL and SSTL output/bidirectional pins in an Arria V device I/O bank. For the I/O placement restrictions for Arria II GX devices, you can refer to the Arria II Device Family Pin Connection Guidelines (PDF). Related Articles Arria II Pin Connection Guidelines: Known Issues Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']