Is there any known issue when simulating Cyclone® V Clock Control Block (ALTCLKCTRL) IP Core and not creating its ena port? - Is there any known issue when simulating Cyclone® V Clock Control Block (ALTCLKCTRL) IP Core and not creating its ena port? Description When simulating a Cyclone® V Clock Control Block (ALTCLKCTRL) IP Core and not creating its ena port, the output clock might not change as expected. This is only a simulation issue. Resolution To work around this issue, and for simulation purposes, please create the ena port and assign a logic high ('1'). This issue will be fixed in a future Quartus® release. Custom Fields values: ['novalue'] Troubleshooting 14025081610 False ['PLL IP'] ['FPGA Dev Tools Quartus® Prime Software Standard'] novalue 22.1 ['Cyclone® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']