Why do the number of I/O pins listed in the Stratix V, Arria V and Cyclone V handbooks for each device variant, differ from the user I/O value provided in the Quartus II software? - Why do the number of I/O pins listed in the Stratix V, Arria V and Cyclone V handbooks for each device variant, differ from the user I/O value provided in the Quartus II software? Description The Stratix® V, Arria® V and Cyclone® V handbooks list the total number of General Purpose I/O (GPIO) available for given device variants. This number does not include the number of Transceiver I/O available. The Quartus® II design software however includes the Transceiver I/O along with the GPIO, in it's total user I/O count, for each device variant. These device families are offered in multiple configurations where the general purpose I/O count is the same, but the number of Transceiver I/O differs depending upon the number of Transceivers in that device variant. It is therefore advised to use the Quartus II software to decipher the total number of I/O available in a device, including Transceiver I/O. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V GS FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']