Error:Top-level design entity “dcp_top” is undefined. - Error:Top-level design entity “dcp_top” is undefined. Description When using the Signal Tap logic analyzer remotely to debug an Accelerator Functional Unit (AFU) on an Intel® Programmable Acceleration Card (PAC) with Intel® Arria® 10 GX FPGA, you may find the AFU project not synthesized. If you compile it using Intel® Quartus Prime Pro Edition software GUI, you may get the errors as below: Error:Top-level design entity “dcp_top” is undefined. Can’t elaborate top-level user hierarchy Flow failed Quartus Prime Synthesis was unsuccessful. 3 errors, 6 warnings. Resolution To work around this issue, you should change your project revision from "afu_fit" to "afu_synth", then you can use Signal Tap II Logic Analyzer to trigger on AFU signal events and capture traces of signals in your AFU design. Custom Fields values: ['novalue'] Troubleshooting 1508368660 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 17.1.1 ['Arria® 10 GX FPGA'] ['novalue'] ['novalue'] ['novalue']