Why does the HVIO pin drive the High state during the configuration stage in the Agilex™ 5 FPGA devices? - Why does the HVIO pin drive the High state during the configuration stage in the Agilex™ 5 FPGA devices? Description Due to a problem in Quartus® Prime Pro Edition Version 25.1 and earlier, you may observe the HVIO pin driving a High state during the configuration stage. Resolution The HVIO Pin driving High state during configuration issue will be fixed starting from the Quartus® Prime Pro Edition Version 25.1.1 and onward. Custom Fields values: ['novalue'] Troubleshooting 15017599822 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.1 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']