Possible Timing Problems With Quarter-Rate DDR3 on Arria V - Possible Timing Problems With Quarter-Rate DDR3 on Arria V Description This problem affects DDR3 products. Due to non-final timing models, the Address and Command versus CK clock relationship, and the DQS versus CK clock relationship can fail timing model checks for quarter-rate DDR3 designs targeting Arria V devices. The resulting design can prove to be not robust in hardware. Resolution The workaround for designs that prove to be not robust in hardware, is to add the following timing constraints to the SDC file: set_clock_uncertainty -from [get_clocks ] -to [get_clocks ] -add -setup 0.400 set_clock_uncertainty -from [get_clocks ] -to [get_clocks ] -add -hold -0.400 The additional timing constraints will make designs more robust across a wider range of fitter seeds; however, timing analysis will still report Address and Command versus CK clock and DQS versus CK clock relationship failures. The additional timing constraints will not be effective on all fitter seeds. This issue will be fixed in a future release. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']