MAX 10 single supply LVDS max data rate - MAX 10 single supply LVDS max data rate Hi all! I work with Intel MAX 10 FPGA, single supply (10M16SAU169I7G) The aim is to implement ADC interface using LVDS - desired speed up to 400 Mbps. I created test project with soft-LVDS and an inspection result shows that timing successfully passed. But, when looking at MAX 10 datasheet ( https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/m10_datasheet.pdf ) p. 53 LVDS Receiver Timing Specifications for Intel MAX 10 Single Supply Devices it states that Data rate for single supply is limited by 290 Mbps. So, which information is correct and how to resolve this contradiction? -- Best regards, Ivan Replies: Re: MAX 10 single supply LVDS max data rate The Quartus does not consider the electrical and switching characteristics. For an IO the limit is put up by the IO standard, structure of the IO and the technology used. Please consider the datasheet value as max data rate. Regards Replies: Re: MAX 10 single supply LVDS max data rate Hi, Ash_R_Intel . Thank you very much for your answer . Well, if so, then it's strange, I suppose, because we need to check in this case for all external interfaces whether our timings exceed the values in the datasheet . I always thought that TQ uses timing data also for the I/O buffer. So what in this case limits the speed? -- Best regards, Ivan Replies: Re: MAX 10 single supply LVDS max data rate Hi, The timing report showed the highest achievable frequency of the internal logic and not the physical limitation of the IO pin. On hardware, the frequency will be limited by the numbers mentioned in the datasheet. Regards Replies: Re: MAX 10 single supply LVDS max data rate Hi, Ash_R_Intel . Yes, it is timing report result after P&R in Quartus TQ. -- Best regards, Ivan Replies: Re: MAX 10 single supply LVDS max data rate Hi, Does inspection result mean timing report number after running place and route in Quartus? The numbers in datasheet are related to hardware characteristics of a high-speed LVDS pin. Regards.