How do I select a data width of 16 bits for the DDR3 SDRAM UniPHY IP in the Cyclone® V EPE IP tab? - How do I select a data width of 16 bits for the DDR3 SDRAM UniPHY IP in the Cyclone® V EPE IP tab? Description The Cyclone® V EPE IP tab is missing the 16-bit data width option for the DDR3 SDRAM UniPHY IP. Resolution Select 32-bit and manually modify the instantiation in the I/O tab (i.e., adjust pin counts - # dq pin, #dqs pins ) to create a 16-bit instantiation. Reuse the entries from the 32-bit option for the CLK, PLL, RAM, and Logic tabs to estimate 16-bit power. Custom Fields values: ['novalue'] Troubleshooting NA False ['DDR3 SDRAM Controller with UniPHY IP'] ['FPGA Dev Tools Quartus® Prime Software Standard'] novalue 13.0 ['Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']