Manual assignment of PLLCLKOUT pin for the MAX 10 device generates errors - Manual assignment of PLLCLKOUT pin for the MAX 10 device generates errors Description In the Quartus® II software release version 14.0 update 2, manual assignment of PLLCLKOUT pin for the MAX® 10 device generates the following errors in the Fitter: Error (176138): Can't place differential I/O pins and/or associated SERDES transmitters or receivers -- location assignments are illegal Error (176150): Pin "< pin name >" with LVDS I/O standard must be driven by the external clock output of an enhanced PLL The PLLCLKOUT pin can be used as general purpose I/O pins for MAX 10 devices, but this option is currently not automatically supported by the Fitter. Resolution There is no workaround. This issue will be fixed in a future release of the Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 14.1 14.0.2 ['MAX® II CPLDs'] ['novalue'] ['novalue'] ['novalue']