Critical Warning Displays if RapidIO IP Core System Clock and Reference Clock Have Same Source - Critical Warning Displays if RapidIO IP Core System Clock and Reference Clock Have Same Source Description If the system clock and the reference clock for your RapidIO MegaCore function are driven by the same source, the Quartus II software issues a critical warning. This issue has no design impact. The critical warning can be ignored. Resolution You can avoid the critical warning by cutting some of the nodes in the Synopsys Design Constraints File ( .sdc ). To obtain an . sdc compatible list of the nodes to be cut, refer to Altera solution rd07132010_207 at www.altera.com/support/kdb/solutions/rd07132010_207.html . This issue will be fixed in a future version of the RapidIO MegaCore function. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 10.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']