Error: ../../../../pcie_ed_rp/ip/pcie_top/pcie/intel_rtile_pcie_ast_300/sim/pcie_intel_rtile_pcie_ast_300_mqi6v2a.sv(63124): Module 'rtile_s20_v0' is not defined - Error: ../../../../pcie_ed_rp/ip/pcie_top/pcie/intel_rtile_pcie_ast_300/sim/pcie_intel_rtile_pcie_ast_300_mqi6v2a.sv(63124): Module 'rtile_s20_v0' is not defined Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1 and earlier, the error below will be seen when using Questasim* Intel® FPGA Edition to simulate a design that instantiates the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express*. Error: ../../../../pcie_ed_rp/ip/pcie_top/pcie/intel_rtile_pcie_ast_300/sim/pcie_intel_rtile_pcie_ast_300_mqi6v2a.sv(63124): Module 'rtile_s20_v0' is not defined Resolution To work around this problem, use the Siemens* Questa* Advanced Simulator full version . This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Edition Software. Custom Fields values: ['novalue'] Errata 14015670023 False ['Interfaces'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.2 21.3 ['Agilex™ 7 FPGA I-Series'] ['Simulation Dev Tools Questa'] ['novalue'] ['novalue']