Why are the stable and resolution valid bits within the Status register of the Clocked Video Input II Intel® FPGA IP stuck at 0? - Why are the stable and resolution valid bits within the Status register of the Clocked Video Input II Intel® FPGA IP stuck at 0? Description Due to a problem with the Clocked Video Input II (4K Ready) Intel® FPGA IP in Intel® Quartus® Prime Software version 17.0 software, you may observe the above problem if you are using embedded synchronization mode. Resolution There is no workaround for this problem. Custom Fields values: ['novalue'] Troubleshooting 1507360943 False ['Clocked Video Input II (4K Ready) IP'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] novalue 17.0 ['Arria® II FPGAs', 'Arria® V FPGAs and SoCs', 'Cyclone® IV FPGAs', 'Cyclone® V FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 LP FPGA', 'Stratix® IV FPGAs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']