Qsys Pro Does Not Support VHDL Generation for Synthesis and Simulation - Qsys Pro Does Not Support VHDL Generation for Synthesis and Simulation
Description The Quartus ® Prime Pro Edition software\'s Qsys Pro beta feature does not support VHDL generation for synthesis and simulation. Resolution Generate your synthesis and simulation files in Verilog.
Custom Fields values:
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Troubleshooting
FB370907;
True
['Simulation']
['FPGA Dev Tools Quartus® Prime Software Pro']
16.1
16.0
['Programmable Logic Devices']
['novalue']
['novalue']
['novalue'] - 2021-08-25
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