Why does the R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* fail to Generate HDL in the IP Parameter Editor Pro - Why does the R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* fail to Generate HDL in the IP Parameter Editor Pro Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2 and earlier, you may see the error message below if your design includes the R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* IP with MSI-X support for PF0 enabled when executing 'generate HDL' in the IP Parameter Editor Pro. Error: intel_rtile_pcie_ast_0: Parameters hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_msix_table_offset_reg_pci_msix_bir hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_msi_enable with values 2 disable failed in satisfying rule rnra_rnr_pcie_ip16::pf0_msix_table_offset_reg_pci_msix_bir_rule Error: intel_rtile_pcie_ast_0: Parameters hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_msix_table_offset_reg_pci_msix_bir hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_msi_enable with values 2 disable failed in satisfying rule rnra_rnr_pcie_ip16::pf0_msix_table_offset_reg_pci_msix_bir_rule Error: qsys-generate failed with exit code 1: 2 Errors, 0 Warnings Resolution To work around this problem, enable MSI and MSI-X support on PF0 to successfully generate HDL code for your IP configuration. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 22.3. Custom Fields values: ['novalue'] Errata 15011394478 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.3 22.2 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue'] - 2022-11-01