Why does the Intel® Stratix® 10 Interlaken (2nd Generation) Intel® FPGA IP Example Design fail in non-continuous mode (Transfer Mode selection set to packet)? - Why does the Intel® Stratix® 10 Interlaken (2nd Generation) Intel® FPGA IP Example Design fail in non-continuous mode (Transfer Mode selection set to packet)? Description Due to a problem with the Intel® Stratix® 10 Interlaken (2nd Generation) Intel® FPGA IP Example Design Packet Transfer mode pattern generator may generate incorrect payload data if the signal itx_ready deasserts during the last packet transfer (i.e. packet 100). Resolution To work around this problem using Intel® Quartus® Prime v19.1 modify the files " ilk_pkt_gen.sv " and " ilk_pkt_gen_mseg.sv " found in the folder /<your example design>/example_design_s10/rtl/ as shown below. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Software. ilk_pkt_gen.sv Change From: always @(posedge clk) begin if (tx_usr_srst_r[0]) begin stop_pkt <= 1'b0; end else if (pkt_cnt == 7'd100 && !continuous_pkt ) begin // end else if (pkt_cnt[6] & pkt_cnt[5] & pkt_cnt[2]) begin stop_pkt <= 1'b1; end end Change To: always @(posedge clk) begin if (tx_usr_srst_r[0]) begin stop_pkt <= 1'b0; end else if (pkt_cnt == 7'd100 && !continuous_pkt && tx_eopbits_nxt[3] ) begin // end else if (pkt_cnt[6] & pkt_cnt[5] & pkt_cnt[2]) begin stop_pkt <= 1'b1; end end ilk_pkt_gen_mseg.sv Change From: always @(posedge clk) begin if (tx_usr_srst_r[0]) begin stop_pkt <= 1'b0; end else if (pkt_cnt_sop == 7'd100 && !continuous_pkt ) begin // end else if (pt_cnt[6] & pkt_cnt[5] & pkt_cnt[2]) begin stop_pkt <= 1'b1; end end Change To: always @(posedge clk) begin if (tx_usr_srst_r[0]) begin stop_pkt <= 1'b0; end else if (pkt_cnt_sop == 7'd100 && !continuous_pkt && (state == ST_C3) && tx_ready ) begin // end else if (pkt_cnt[6] & pkt_cnt[5] & pkt_cnt[2]) begin stop_pkt <= 1'b1; end end Custom Fields values: ['novalue'] Troubleshooting 1507266551 True ['Interlaken (2nd Generation) IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 19.1 ['Stratix® 10 FPGAs and SoCs', 'Stratix® 10 GX FPGA', 'Stratix® 10 MX FPGA', 'Stratix® 10 SX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']