UDP/IP Offload Engine - Chevin Technology’s UDP Ethernet IP core delivers low‑latency, high‑throughput connectivity across 10G–200G networks, with efficient packet handling and minimal overhead. It simplifies integration… Chevin Technology is an IP designer and vendor based in Cambridge, United Kingdom. Our Cybersecurity and Ethernet protocol accelerator IP products for Altera FPGAs help our customers develop FPGA… Cyclone® III FPGA Agilex™ 9 FPGA Direct RF-Series MAX® V CPLD Stratix® IV E FPGA Stratix® IV GX FPGA MAX® 10 FPGA Stratix® V GS FPGA Stratix® V GX FPGA Stratix® III FPGA User Datagram Protocol (UDP/IP) is a communications protocol used for establishing connections between applications on the Internet. The UDP Protocol is a transport layer that runs on top of the Internet Protocol (IP) Layer and is used for connections where high sustained throughput is a priority and some data loss is expected, such as with video and audio streaming. Chevin Technology’s 10G /25G/40G/100G UDP Ethernet IP core for FPGAs has low latency and bandwidth overhead, as it sends packets of data without confirming receipt. De-fragmentation is available as an option, so large UDP datagrams can be easily sent and received. The UDP IP core provides individual port numbers to differentiate between user requests, and receipt of data is verified using the checksum functionality. Chevin Technology’s 10G /25G/40G/100/200G UDP Ethernet IP core is configurable for FPGAs and simplifies integration by handling the complete Ethernet frame assembly. Chevin Technology’s UDP IP core is a mature IP core with proven success in customers’ projects. Reference designs are available for various boards to assist with integration and we offer our customers bespoke, expert engineering support packages to help meet their project goals. A simple AXI4 streaming interface is all that is required to start sending and receiving UDP datagrams, and only the user data payload is exchanged between the application and the UDP core. For a single port application the port number can be set to a constant, hard coded or software configurable. A multi-port application is supported by a single UDP IP core by using the TDEST sideband embedded in the streaming interface. Ethernet Aerospace Broadcast Data Center Cloud (Public, Private, Hybrid) Defense Industrial Medical UDP/IP Offload Engine Key Features AXI4s MAC & Application Interfaces Offering Brief No Yes No Yes Encrypted VHDL Cyclone® III FPGA Agilex™ 9 FPGA Direct RF-Series MAX® V CPLD Stratix® IV E FPGA Stratix® IV GX FPGA MAX® 10 FPGA Stratix® V GS FPGA Stratix® V GX FPGA Stratix® III FPGA Yes Yes 25.3.1 Offering Brief Production a1JUi0000049U7SMAU What's Included RTL – encrypted source/netlist , Documentation – Data Sheet and User Guide, Simulation – Test Bench and example use cases with vector generation Ordering Information CT-UDP_OFFLOAD_ENGINE a1JUi0000049U7SMAU Production Intellectual Property (IP) a1MUi00000BO8rSMAT a1MUi00000BO8rSMAT Select 2026-05-27T20:10:25.000+0000 Chevin Technology’s UDP Ethernet IP core delivers low‑latency, high‑throughput connectivity across 10G–200G networks, with efficient packet handling and minimal overhead. It simplifies integration with an AXI4‑Streaming interface, supports multi‑port configurations, and provides a proven, scalable solution for high‑performance networking applications. Partner Solutions