Error (20834): When you enable the CvP setting, you must make sure design is CvP capable. - Error (20834): When you enable the CvP setting, you must make sure design is CvP capable. Description Due to an enhancement in the Intel® Quartus® Prime Pro Edition Software version 21.2, the error message shown above will be seen during compilation if the Configuration via Protocol (CvP) CvP Settings in Device and Pin Options is set to Initialization and Update but the option Enable_CvP (Intel_VSEC) is not checked in the Intel® FPGA F-Tile Avalon® Streaming IP for PCI Express, R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express or in the P-Tile Intel® FPGA IP for PCI Express core. Resolution To work around this problem, enable the following settings to use the CvP feature: Set CvP settings to Initialization and update in Device and Pin options . Enable the option Enable CVP (Intel VSEC) in the Intel® FPGA F-Tile Avalon® Streaming IP for PCI Express, R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express or in the P-Tile Intel® FPGA IP for PCI Express core. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.2. Custom Fields values: ['novalue'] Troubleshooting 1508682305 False ['Avalon-MM Stratix® 10 Hard IP for PCI Express', 'Avalon-ST Stratix® 10 Hard IP for PCI Express', 'PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.2 21.2 ['Agilex™ 7 FPGA F-Series', 'Agilex™ 7 FPGA I-Series', 'Stratix® 10 DX FPGA'] ['novalue'] ['novalue'] ['novalue']