Error: Logic Generation failed to load results from Design Analysis and cannot get the list of IPs in the design - Error: Logic Generation failed to load results from Design Analysis and cannot get the list of IPs in the design Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 or earlier, you might see this error message during the Support-Logic Generation stage when compiling a design on the Windows* Operating System. This error occurs when Windows* long path support is disabled. Windows* limits the combined length of a file name and its path to 260 characters. If the project path exceeds this limit, the Quartus® Software cannot access required IP or design files. Resolution To work around this problem, enable Windows* long path support by updating the registry: a) Open Registry Editor: Press Windows Key + R , type regedit , and press Enter. b) Navigate to HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Control\FileSystem c) Find LongPathsEnabled. Double-click it and set "Value data" to 1 . If the LongPathsEnabled doesn't exist, right-click, select New > DWORD (32-bit) Value , and name it LongPathsEnabled. d) Restart your computer. This error message will be enhanced in a future release of the Quartus ® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting QS-26928 novalue ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.3 ['Agilex™ 3 FPGAs and SoCs', 'Agilex™ 5 FPGAs and SoCs', 'Agilex™ 7 FPGAs and SoCs', 'Agilex™ 9 FPGA Direct RF-Series', 'Agilex™ 9 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Arria® 10 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']