How do I program the dynamic I/O delay chains using the ALTIOBUF megafunction in Stratix V, Arria V, and Cyclone V devices? - How do I program the dynamic I/O delay chains using the ALTIOBUF megafunction in Stratix V, Arria V, and Cyclone V devices? Description Follow these instructions to program the dynamic I/O delay chains using the ALTIOBUF megafunction in Stratix® V, Arria® V, and Cyclone® V devices. Each IOE programmable delay transaction requires 40 clock cycles with io_config_clkena asserted. The LSB should be your first bit (io_config_datain[0]) at the beginning of your transaction. You can find the bit format information for each device family in the ALTDQ_DQS2 Megafunction User Guide (PDF) . Use table 4-1 for Stratix V devices, table 4-3 for Arria V, and Cyclone V devices. Each IOE programmable delay is 6 bits wide. The reserved bits should be set to zero. The io_config_update should be asserted after the 40 th clock cycle. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']