Why does the HDMI Intel® FPGA Sink IP locked signal stay asserted when the HDMI cable is unplugged ? - Why does the HDMI Intel® FPGA Sink IP locked signal stay asserted when the HDMI cable is unplugged ? Description Due to a problem starting in version 20.4 of the Intel® Quartus® Prime Pro software, the HDMI Intel® FPGA Sink IP locked signal will continue to assert high when the HDMI cable is unplugged. This is due to the HDMI Intel® FPGA Sink IP locked signal reset mechanism being clocked by the HDMI cable TMDS clock which will absent once HDMI cable is unplugged. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 21.2 where the HDMI Intel® FPGA Sink IP locked signal would be deasserted when the HDMI cable is unplugged. Custom Fields values: ['novalue'] Troubleshooting 1509044796 1508865062 True ['HDMI IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.2 20.4 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']