Error(17821): Netlist error at <name>_avst_credit_pipeline_0.vhd(): port snk_in_empty of width n cannot connect to m bit actual - Error(17821): Netlist error at <name>_avst_credit_pipeline_0.vhd(): port snk_in_empty of width n cannot connect to m bit actual Description Due to a problem in the Intel® Quartus® Prime Pro edition software, you may see this error when compiling a design that includes the Avalon®-ST Credit Pipeline IP. The error occurs when Use Empty, Use Channel or Use Error are disabled and the associated port width is not set to 1. This problem also only affects Platform Designer systems generated in VHDL. Resolution To work around this problem, either generate the Platform Designer system in Verilog HDL or ensure width of the unused port is set to 1. This problem is fixed beginning with version 20.2 of the Intel® Quartus® Prime Pro edition software. Custom Fields values: ['novalue'] Troubleshooting 22010488406 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.2 20.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']