Why does the Intel® Stratix® 10 L/H-Tile PCIe* Endpoint's Transaction Layer get stuck in reset when Function-Level Reset FLR is initiated? - Why does the Intel® Stratix® 10 L/H-Tile PCIe* Endpoint's Transaction Layer get stuck in reset when Function-Level Reset FLR is initiated? Description When Function-Level Reset (FLR) capability is disabled, a Configuration Write setting the Device Control Register's parameter Initiate Function-Level Reset to 1 will cause the Intel® Stratix® 10 L/H-Tile PCIe* Endpoint's Transaction Layer to be stuck in reset. The Intel® Stratix® 10 L/H-Tile PCIe* Endpoint will respond to subsequent requests with Unsupported Request (UR) TLP. Conventional reset is needed to recover from this error case, e.g., PERST#, Hot Reset, or Link Disable/Enable. Resolution To work around this problem, enable FLR capability in the IP Parameter Editor. Custom Fields values: ['novalue'] Troubleshooting 2205931877 False ['Avalon-MM Stratix® 10 Hard IP for PCI Express', 'Avalon-ST Stratix® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 18.0 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']