Why is the timestamp accuracy error of PTP designs with the 25G Ethernet Intel® Stratix® 10 FPGA IP higher than expected? - Why is the timestamp accuracy error of PTP designs with the 25G Ethernet Intel® Stratix® 10 FPGA IP higher than expected? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software Version 22.4, PTP designs using the 25G Ethernet Intel® Stratix® 10 FPGA IP may observe higher timestamp accuracy error values in both simulation and hardware. This problem will impact 10G and 25G rates. Resolution To work around this problem in the Intel® Quartus® Prime Pro Edition Software v22.4, compensate the timestamp accuracy error by adding the following value on top of the configured RX PMA latency value in the CSR r egister 0xB06 (RX_PTP_PMA_LATENCY): - 25G mode: Add 2.56ns (one clk_rxmac clock cycle) - 10G mode: Add 6.4ns (one clk_rxmac clock cycle) This problem has been fixed in version 23.1 of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15012487487 False ['IP Low Latency 25-Gbps Ethernet MAC and PHY Function IP-25GEUMACPHY'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.1 22.4 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']