set_max_skew constraint might not properly constrain the design - set_max_skew constraint might not properly constrain the design Description In the Quartus ® II software versions 11.0, in the TimeQuest Timing Analyzer, the rise_from_clock , rise_to_clock , fall_from_clock and fall_to_clock options of the set_max_skew constraint do not properly constrain the design. Resolution Use the from_clock and to_clock options and use an explicit clock collection instead of "*" . For example, use [get_clocks *] or [all_clocks] instead of "*" . This issue is corrected in the Quartus II software version 11.0 SP1. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 11.0.1 11.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue'] - 2021-08-25