Rule C105: Clock signal should be a global signal - Rule C105: Clock signal should be a global signal Description You may see the following warnings when running the Design Assistant tool in Quartus® II software on your compiled HPS design. Resolution Rule C105: Clock signal should be a global signal ; <hierarchy>|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|afi_clk Rule C105: Clock signal should be a global signal ; <hierarchy>|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk Custom Fields values: ['novalue'] Troubleshooting 1408190367 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 14.1 ['Arria® V GT FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']