Why are the Timestamp interface signals of the Triple-Speed Ethernet Intel® FPGA IP for Intel Agilex® 7 FPGA with "10/100/1000Mb Ethernet MAC" core variation with Timestamping enabled are not exported? - Why are the Timestamp interface signals of the Triple-Speed Ethernet Intel® FPGA IP for Intel Agilex® 7 FPGA with "10/100/1000Mb Ethernet MAC" core variation with Timestamping enabled are not exported? Description The Triple-Speed Ethernet Intel® FPGA IP for Intel Agilex® 7 FPGA E-Tile and F-Tile with "10/100/1000Mb Ethernet MAC" core variation does not support Precision Time Protocol (PTP) configuration. Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.3 and 22.4, the Triple-Speed Ethernet Intel® FPGA IP for Intel Agilex® 7 E-Tile and F-Tile with "10/100/1000Mb Ethernet MAC" core variation has "Enable Timestamping" option incorrectly exposed in the GUI when the "Enable Internal FIFO" option is un-checked. This behavior is not intended, and the generated RTL files do not support PTP operation. Resolution You should not generate the design for the "10/100/1000Mb Ethernet MAC" core variation with the "Enable Timestamping" option enabled. This problem has been fixed in the Intel® Quartus® Prime Pro Edition Software version 23.1. Custom Fields values: ['novalue'] Troubleshooting 15012849880 False ['Triple-Speed Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.1 22.3 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']