Why does the Intel® Quartus® synthesis compilation show missing "sdi_cvo_rden" port error when two Clocked Video Output (CVO) II IP core are instantiated in the Intel® Quartus® design ? - Why does the Intel® Quartus® synthesis compilation show missing "sdi_cvo_rden" port error when two Clocked Video Output (CVO) II IP core are instantiated in the Intel® Quartus® design ? Description Due to the problem in the Intel® Quartus® Prime Pro version 19.2 software and later, the sdi_cvo_rden port is available once " embedded in video " option is checked in Clock Video Output (CVO) II IP core. The Intel® Quartus® synthesis stage of compilation will fail with missing "sdi_cvo_rden" port error when two or more CVO II IP are instantiated in the Intel® Quartus® design. Resolution No work around to this problem exists. This problem has been fixed starting in version 20.2 of the Intel® Quartus® Prime Pro software. Custom Fields values: ['novalue'] Troubleshooting 1507949444 True ['Clocked Video Output II (4K Ready) IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.2 19.2 ['Agilex™ 7 FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']