IntelliProp SAS Initiator IP Core (IPC-SS105A-HI) - The "Commander" of the SAS interface, providing a high-performance SAS 3.0 compliant Initiator IP core (3.0/6.0/12.0 Gb/s) designed for robust, enterprise-grade control of complex storage topologies. IntelliProp is the industry's Strategic Gatekeeper for high-assurance memory and data storage. We provide "Gold Standard" IP cores and expert design services for NVMe, SATA, SAS, and AES-XTS security… Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Cyclone® V GX FPGA Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA The IPC-SS105A-HI is a comprehensive Serial-Attached SCSI (SAS) Initiator solution that allows Altera FPGAs to act as the primary controller for high-density storage ecosystems. Unlike simplified bridge solutions that only offer point-to-point connectivity, this core provides the robust protocol depth required to manage complex SAS/SATA topologies, including full support for SAS Expanders. It manages the entire protocol stack—PHY, Link, Port, and Transport layers—and supports both SSP and STP (SATA Tunneling Protocol), giving developers the flexibility to command both high-reliability SAS and cost-effective SATA drives within a single enterprise environment. Access Aerospace ASIC Proto Broadcast Consumer Data Center Cloud (Public, Private, Hybrid) Defense Government Medical Test Transportation IntelliProp SAS Initiator IP Core (IPC-SS105A-HI) Key Features Multi-Protocol Support: Full support for SSP (SAS) and STP (SATA) targets. Offering Brief Yes Yes No Yes Encrypted Verilog Encrypted VHDL Verilog VHDL Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Cyclone® V GX FPGA Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Yes Yes 25.3.0 Offering Brief Production a1JUi0000049UFYMA2 What's Included Encrypted Verilog RTL Ordering Information IPC-SS105A-HI a1JUi0000049UFYMA2 Production Intellectual Property (IP) a1MUi00000BO8sHMAT a1MUi00000BO8sHMAT Select 2026-04-21T12:58:32.000+0000 The "Commander" of the SAS interface, providing a high-performance SAS 3.0 compliant Initiator IP core (3.0/6.0/12.0 Gb/s) designed for robust, enterprise-grade control of complex storage topologies. Partner Solutions