Why is the tx_ready_err CSR register bit flagged after the JESD204C Intel® FPGA IP is reset in the Intel® Stratix® 10 devices? - Why is the tx_ready_err CSR register bit flagged after the JESD204C Intel® FPGA IP is reset in the Intel® Stratix® 10 devices? Description After the JESD204C Intel® FPGA IP link is up in Intel® Stratix® 10 devices, if there is a warm reset applied to the IP, an unexpected tx_ready_err CSR register bit might be flagged right after the IP is reset. This is due to the transceiver getting reset and tx_ready being deasserted after the mgmt_clk (avs_clk domain) is out of reset. Resolution To work around this problem do either of the following: Clear the error interrupt. To avoid the interrupt, prolong the mgmt_clk (avs clk domain) reset when there is an IP reset to avoid errors being flagged during the reset period. This problem is fixed starting from the Intel® Quartus® Prime Pro Edition Software version 19.3. Custom Fields values: ['novalue'] Troubleshooting 1507271106, 1507271106 True ['JESD204B IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.3 19.2 ['Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']