Is DCLK a dual-purpose pin in Stratix V, Arria V and Cyclone V devices? - Is DCLK a dual-purpose pin in Stratix V, Arria V and Cyclone V devices? Description No, DCLK is not a dual-purpose pin in the Stratix® V, Arria® V and Cyclone® V device familes, so it is not possible to manually assign a user signal to this pin in the Quartus® II design software. However, if using the ALTASMI_PARALLEL megafunction or the EPCS Controller component in QSys, DCLK will be accessible by these functions in user mode, to faciliate access to an EPCS or EPCQ device. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']