Error: pcie_hard_ip_0_pcie_bfm_0: altera_pcie_bfm_qsys does not support generation for VHDL Simulation. Generation is available for: Verilog Simulation, Quartus Synthesis - Error: pcie_hard_ip_0_pcie_bfm_0: altera_pcie_bfm_qsys does not support generation for VHDL Simulation. Generation is available for: Verilog Simulation, Quartus Synthesis Description You may encounter this error when you attempt to generate a VHDL testbench for the Stratix® IV IP Compiler for PCI Express® under Qsys. Resolution To avoid this error, use Verilog HDL for the testbench. The VHDL testbench is not available for Stratix IV designs. This problem is not scheduled to be fixed. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 13.0.1 ['Stratix® IV GT FPGA', 'Stratix® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']