Why to burst transfers from a lineWrap enabled master fail? - Why to burst transfers from a lineWrap enabled master fail? Description Burst transfers from an Avalon®-MM master which has the lineWrap parameter set may access the incorrect addresses when the burst begins from an address which is not aligned with a burst boundary. This problem occurs when there are 2 or more Avalon-MM masters connected to a slave. The problem causes the Qsys fabric to miscalculate the burst boundary and so not wrap at a burst boundary. For more information on the lineWrap parameter, refer to chapter 3 of the Avalon Interface Specifications (PDF) . An example of an Avalon-MM master with the lineWrap parameter enabled is the Nios® II instruction_master. Resolution This problem is fixed beginning with version 13.0 of the Quartus® II software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['Nios® II Processor'] ['FPGA Dev Tools Quartus II Software'] 13.0 11.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']