Why don't I see Dual Simplex IP generation and compilation error with simplex configuration using GTS PMA/FEC Direct PHY FPGA IP? - Why don't I see Dual Simplex IP generation and compilation error with simplex configuration using GTS PMA/FEC Direct PHY FPGA IP? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.2, you will not see any errors if you implement a dual simplex interface using GTS PMA/FEC Direct PHY FPGA IP. Dual simplex mode is supported for the simplex protocols specified in section 2.0 of the GTS Transceiver Dual Simplex Interfaces User Guide, not custom simplex interfaces with GTS PMA/FEC Direct PHY FPGA IP. Avoid using dual simplex mode with GTS PMA/FEC Direct PHY FPGA IP in your design. Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition software version 24.3. Custom Fields values: ['novalue'] Troubleshooting 15016210189 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3 24.2 ['Agilex™ 5 FPGA E-Series'] ['novalue'] ['novalue'] ['novalue']