Why does niosv-download return “Invalid reset option” when executing reset from debug module? - Why does niosv-download return “Invalid reset option” when executing reset from debug module? Description Due to a problem in the Ashling RiscFree IDE for Altera® software, the niosv-download returns “Invalid reset option” when executing reset from debug module for designs targeting Nios ® V processor. The affected versions are: Software version 25.2.1 (version dated 9 th May 2025, paired with Quartus® Prime Pro software version 25.1.1 and Quartus® Prime Standard software version 25.1) Software version 25.3.1 (version dated 1 st Aug 2025, paired with Quartus® Prime Pro software version 25.3.1) Software version 25.4.1 (version dated 31 st Oct 2025, paired with Quartus® Prime Pro software version 26.1) The problem is caused by Ashling GDBServer failing to execute software reset (swreset), and niosv-download is using Ashling GDBServer to communicate with the processor. Thus, this failure prompts the “Invalid reset option” message when executing “niosv-download –r". Resolution To work around this problem, use the argument “-o” to change from Ashling GDBserver to OpenOCD. $ niosv-download –r -o This problem is fixed beginning with the Ashling RiscFree IDE for Altera® Quartus® software version 26.1.1-C, which is paired with Quartus® Prime Pro software version 26.1.1. Related Articles NIOS V/m dbg_reset_out signal (Q25.1 Std, MAX10) | Altera Community - 352387 Custom Fields values: ['novalue'] Troubleshooting QS-166103 novalue ['Soft Embedded Processors RISC-V NIOS V (Primary)'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] novalue 25.1.1 ['Agilex™ 3 FPGAs and SoCs', 'Agilex™ 5 FPGAs and SoCs', 'Agilex™ 7 FPGAs and SoCs', 'Agilex™ 9 FPGA Direct RF-Series', 'Agilex™ 9 FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Arria® II FPGAs', 'Arria® V FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Cyclone® 10 LP FPGA', 'Cyclone® IV FPGAs', 'Cyclone® V FPGAs and SoCs', 'MAX® 10 FPGAs', 'MAX® II CPLDs', 'MAX® V CPLDs', 'Stratix® 10 FPGAs and SoCs', 'Stratix® IV FPGAs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']